A CPU has a 32 KB direct-mapped cache with a 128-byte block size. Array A is a…

A CPU has a 32 KB direct-mapped cache with a 128-byte block size. Array A is a two-dimensional 512 × 512 array whose elements occupy 8 bytes each. Consider the following C code segment P1: Assume that A[0][0] is aligned to a 128-byte cache-block boundary.

 
for (i=0; i<512; i++) {
   for (j=0; j<512; j++) {
      x += A[i][j];
   }
} 

The second code segment P2 is:

 
for (i=0; i<512; i++) {
   for (j=0; j<512; j++) {
      x += A[j][i];
   }
}

P1 and P2 are executed independently from the same initial state: no block of A is in the cache, and i, j, and x are held in registers. Let M1 and M2 denote the numbers of cache misses for P1 and P2, respectively. The value of M1 is: