Which one of the following statements is FALSE?

Answer: The memory access time using a given inverted page table is always same for all incoming virtual addresses.

Explanation: Review of each statement and why the highlighted statement is false.

• "The TLB performs an associative search in parallel on all its valid entries using page number of incoming virtual address."

  Why this is true: A TLB is a small associative cache keyed by page number; it checks all valid entries in parallel and returns the frame number on a hit, giving fast translation.

• "If the virtual address of a word given by CPU has a TLB hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory."

  Why this is true: A TLB hit indicates a valid page-to-frame mapping (the page is resident), so if the CPU cache misses, the data is fetched from main memory rather than from disk.

• "The memory access time using a given inverted page table is always same for all incoming virtual addresses."

  Why this is false: Inverted page tables typically use a global lookup mechanism such as hashing. Hash collisions, different chain lengths or probe counts, and implementation details cause lookup latency to vary by virtual address. Therefore access time is not guaranteed to be constant for all addresses.

• "In a system that uses hashed page tables, if two distinct virtual addresses V1 and V2 map to the same value while hashing, then the memory access time of these addresses will not be the same."

  Why this is true: When hashing produces a collision, entries are resolved by chaining or probing; the position within the chain or probe sequence can make one lookup slower than another.

Conclusion: The third statement about inverted page table access time being identical for all virtual addresses is false because hashing and collision resolution introduce variable lookup costs.