Register & Bus Organization MCQs: 12 Solved Questions with Explanations

Register questions can look like simple recall, but their distractors blur storage location, register role, bus width, bus implementation and transfer control. Separate five cues before choosing: what is stored, which register owns the role, how many bits move in parallel, how one bus source is selected, and which control signal enables the transfer. Use the wider GATE CS Exam Preparation page to place register transfers within the full subject plan. Commit to an option and state the governing idea before reading each explanation.

Register and bus organization: the working model before the MCQs

Registers are fast storage inside the CPU. The Program Counter (PC) identifies the next instruction address, the Instruction Register (IR) holds the instruction being executed, the Memory Address Register (MAR) holds a memory address, and the Memory Buffer Register or Memory Data Register (MBR or MDR) holds a transferred memory word. A bus is a shared set of signal lines; its width is the number of parallel data lines. A disabled tri-state driver presents high impedance, an effectively disconnected output.

Now build a common bus for eight 16-bit registers, R0 to R7. Each of the 16 bus bit positions must select one corresponding bit from eight sources, so the circuit needs 16 parallel 8-to-1 multiplexers. The selector needs three lines because log2(8) = 3. If R5 = 0x3A6C and S2S1S0 = 101, binary 101 selects register 5, so the bus carries 0x3A6C. When LOAD R2 is asserted, the active clock edge stores 0x3A6C in R2.

Register & Bus Organization MCQs 1-3: storage and micro-operations

Question 1

UPLT 2018, Computer Science

Which of the following is not true regarding registers?

• A. Internal storage of CPU

• B. Can hold either data or instruction

• C. Made up of flip-flop

• D. Cannot store intermediate results

Answer: D.

Registers are internal CPU storage built from flip-flop circuits. They can hold data, instructions, addresses and intermediate results, so A, B and C are true while D is not.

Question 1 solution.

Question 2

MPPSC 2025, Computer Science

Some operations require the control unit to store data temporarily. _____ are some temporary storage location in the CPU that are designed for this purpose.

• A. RAMs

• B. ROMs

• C. Registers

• D. Hard Drives

Answer: C.

Registers sit inside the CPU and retain values needed during execution. RAM and ROM are memory components, while a hard drive is secondary storage. The stated location therefore identifies a register.

Question 2 solution.

Question 3

ISRO 2023, Computer Science

The operation executed on data stored in registers is called

• A. Macro-operation

• B. Micro-operation

• C. Bit-operation

• D. Byte-operation

Answer: B.

A micro-operation is an elementary operation on information stored in registers, such as transfer, addition, shifting or logic. Bit-operation and byte-operation may describe granularity, but neither is the standard computer-organisation term.

Question 3 solution.

Register & Bus Organization MCQs 4-6: IR, PC and IBR roles

Question 4

DSSSB 2024, TGT, Computer Science

In CPU, which of the following type of register is required by the control unit and contains the instruction currently being executed?

• A. Instruction register

• B. Accumulator

• C. Program register

• D. Memory data register

Answer: A.

The IR holds the current instruction while the control unit decodes it. An accumulator holds arithmetic values, while the memory data register buffers a transferred word. "Currently being executed" identifies the IR.

Question 4 solution.

Question 5

DSSSB 2021, PGT, Computer Science

What is the function of the program counter register?

• A. It holds the operand address

• B. It holds the address of current instruction

• C. It holds the address of previous instruction

• D. It holds the address of next instruction

Answer: D.

The PC identifies the next instruction address. It advances sequentially or receives a branch target, while the current instruction belongs in the IR. That separates D from B.

Question 5 solution.

Question 6

UPPSC Polytechnic Lecturer 2022, Computer Science

Which of the following register is employed to hold temporarily the right-hand instruction from a word in memory?

• A. Instruction Register (IR)

• B. MAR

• C. AC and MQ

• D. IBR

Answer: D.

In the packed two-instruction word organisation assumed here, the IBR holds the right-hand instruction while the left-hand one executes. IR holds the current instruction, MAR holds an address, and AC and MQ have arithmetic roles.

Question 6 solution.

Register & Bus Organization MCQs 7-9: bus structure, width and multiplexers

Question 7

HPSC 2021, Computer Science

The main virtue for using single Bus structure is

• A. fast data transfers

• B. cost effective connectivity and speed

• C. cost effective connectivity and ease of attaching peripheral devices

• D. cheaper in price

Answer: C.

A single bus reduces interconnection hardware and gives devices a common attachment path. Competing transfers are serialised, so speed is not its main virtue. C captures the connectivity advantage without a false speed claim.

Question 7 solution.

Question 8

DSSSB 2018, Computer Science

The number of lines used in a data bus is referred to as the ____ of the data bus.

• A. length

• B. density

• C. width

• D. volatility

Answer: C.

Bus width is the number of bits carried in parallel, so a data bus with 16 lines is 16 bits wide. Length, density and volatility do not name the line count.

Question 8 solution.

Question 9

UGC NET 2021, Computer Science

A digital computer has a common bus system for 8 registers 16 bits each. How many multiplexers are required to implement common bus? What size of multiplexers is required?

• A. 16, 8x1

• B. 8, 16x1

• C. 8, 8x1

• D. 16, 16x1

Answer: A.

The 16 bus positions need 16 multiplexers, one per bit. Each selects the corresponding bit from eight registers, so its size is 8x1. Three selector lines suffice because 2^3 = 8, giving A.

Question 9 solution.

Register & Bus Organization MCQs 10-12: tri-state control, serial buses and register windows

Question 10

ISRO 2014, Computer Science

The output of a tristate buffer when the enable input is 0 is:

• A. Always 0

• B. Always 1

• C. Retains the last value when enable input was high

• D. Disconnected state

Answer: D.

A disabled tri-state buffer produces high impedance, written Z. It is disconnected, allowing another source to drive the bus. It is neither logic 0 nor logic 1 and retains no value.

Question 10 solution.

Question 11

CDAC CCAT 2017

Which one is correct about serial versus parallel bus?

• A. Parallel bus would be faster than serial bus

• B. Serial bus can be clocked considerably faster than parallel bus, as there is no issue of clock skew between different lines of the bus

• C. Serial bus would be slower than parallel bus

• D. None of the above

Answer: B.

At high rates, parallel lines can deliver bits at different times, limiting the safe clock. A serial stream has no lane-to-lane skew, so it can be clocked faster. This does not guarantee lower latency.

Question 11 solution.

Question 12

ISRO 2009, Computer Science

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for:

I. Function locals and parameters

II. Register saves and restores

III. Instruction fetches

• A. I only

• B. II only

• C. III only

• D. I and II only

Answer: D.

Overlapping windows let a caller's output registers become the callee's input registers, reducing memory traffic for parameters and locals. Window switching also reduces saves and restores. Instruction fetching is unaffected, so III is excluded.

Question 12 solution.

The traps these 12 register and bus questions expose

Circle whether the stem asks for a component, role, width or implementation count. Expand each register name before choosing. For a bus numerical, calculate output lines first and source choices second. In a negative stem such as Question 1, mark "not" before reading the options.

For the complete instruction path plus clock and address-line numericals, use CPU Organization Basics MCQs. Register and bus practice here instead concentrates on register roles, micro-operations, common-bus selection and driver control. Next, connect PC, IR and address hardware to Addressing Modes and Instruction Formats. Once those roles are secure, Pipelining in Computer Architecture Explained shows how registers later become pipeline-stage boundaries.

Register & Bus Organization: the next practice step

Retest Questions 4, 6, 9, 10 and 12 without looking. The questions test current-instruction storage, a buffered instruction half, multiplexer construction, high-impedance bus control and overlapping register windows. Write a one-line reason beside every answer, not only the option letter, then retry any item whose reason was vague. If you want a sequenced Computer Organization route that places register transfers beside micro-operations, CPU organisation, memory and pipelining, use GATE Guidance by Sanchit Sir. The short version is simple: first identify what must be stored or transferred, then name the register, count the bus lines, and only after that inspect the distractors.