Multiprocessor Classification MCQs: 8 Solved MCQs and 2 Concept Checks

Multiprocessor classification gets difficult when a stem changes axes. Flynn's taxonomy counts instruction and data streams, coupling follows memory and communication, bus timing follows clocking and handshakes, and performance follows serial work and task precedence. Name the axis before choosing a fact or formula.

Multiprocessor classification MCQs: set the four decision axes first

Use this compact map before solving:

For a serial part Ts and parallel part Tp on n processors, use T(n) = Ts + Tp / n. Then speedup is T(1) / T(n), and efficiency is speedup / n. A precedence graph can impose a longer schedule than this ideal split, so compute its critical levels directly.

The GATE CS exam preparation page places these distinctions in the broader COA route. Start with Flynn's Taxonomy & Computer Classification: 12 Solved MCQs for the broad five-axis map and baseline questions. Then move to multiprocessor coupling, synchronous-bus timing, Amdahl calculations, and precedence-limited efficiency.

Flynn's taxonomy MCQs: order and implementation

Question 1

UGC NET Paper 2 (June), 2020

Arrange the following types of machine in descending order of complexity.

(A) SISD

(B) MIMD

(C) SIMD

Choose the correct answer from the options given below:

• (a) A,B,C

• (b) C,B,A

• (c) B,C,A

• (d) C,A,B

Answer: (c) B,C,A, so the order is MIMD > SIMD > SISD. MIMD coordinates independent instruction and data streams, SIMD applies one instruction stream across several data elements, and SISD has one stream of each. Here, complexity means control and coordination complexity, not guaranteed performance across every implementation.

Question 2

ISRO Computer Science, 2008

Which of the following architecture is/are not suitable for realising SIMD?

• (a) Vector processor

• (b) Array processor

• (c) Von Neumann

• (d) All of the above

Answer: (c) Von Neumann. Vector and array processors naturally apply one operation to several data elements. In the question's textbook framing, a classical sequential Von Neumann processor is the unsuitable choice; modern processors derived from that model may still add SIMD instruction extensions.

Multiprocessor classification MCQs: bus timing, parallelism, and coupling

Question 3

UGC NET Paper 2 (December), 2023

A system bus in which each data item is transferred during a time slice known in advance to both units source and destinations is called :

• (a) MIMD

• (b) DMA

• (c) asynchronous bus

• (d) synchronous bus

Answer: (d) synchronous bus. A common clock gives the source and destination predetermined transfer slots. An asynchronous bus uses handshaking, while DMA identifies who moves data rather than the timing scheme.

Question 4

UP LT Grade Assistant Teacher

To achieve parallelism, one needs a minimum of

• (a) 2 processors

• (b) 3 processors

• (c) 4 processors

• (d) None of the above

Answer: (a) 2 processors. Hardware parallelism requires at least two processing elements to execute work at the same time. A single processor can interleave concurrent tasks, but that time-sharing does not create simultaneous execution on separate processing elements.

Question 5

DSSSB Computer Science, 2021

_____ is loosely coupled system and _____ is tightly coupled system.

• (a) Distributed processing; Uniprocessing

• (b) Batch processing; Parallel processing

• (c) Distributed processing; Parallel processing

• (d) Uniprocessing; Real Processing

Answer: (c) Distributed processing; Parallel processing. Distributed nodes generally keep private memories and communicate by messages, so they are loosely coupled. A shared-memory multiprocessor is tightly coupled; parallel processing is broader in general usage, but this is the conventional contrast intended by the paired options.

Parallel processing performance MCQs: Amdahl's law and precedence

Question 6

ISRO

A particular parallel program computation requires 100 seconds when executed on a single CPU. If 20% of this computation is strictly sequential, then theoretically the best possible elapsed times for this program running on 2 CPUs and 4 CPUs respectively are

• (a) 55 and 45 seconds

• (b) 80 and 20 seconds

• (c) 75 and 25 seconds

• (d) 60 and 40 seconds

Answer: (d) 60 and 40 seconds. The sequential part is 20% of 100 = 20 seconds, while the parallel part is 80 seconds. On two CPUs, T(2) = 20 + 80 / 2 = 60 seconds; on four CPUs, T(4) = 20 + 80 / 4 = 40 seconds.

Question 7

UGC NET Paper 2

A multiprocessor system with 16 processors executes a parallelisable task. The serial portion takes 200 clock cycles and the parallel portion takes 800 clock cycles. How many total clock cycles are required when all 16 processors are used?

• (a) 250

• (b) 300

• (c) 400

• (d) 450

Answer: (a) 250 clock cycles. The serial 200 cycles cannot be divided. The parallel portion takes 800 / 16 = 50 cycles, so total time is 200 + 50 = 250 cycles; dividing all 1,000 cycles by 16 would incorrectly parallelise the serial work.

Question 8

ISRO Computer Science, 2011

Below is the precedence graph for a set of tasks to be executed on a parallel processing system S.

What is the efficiency of this precedence graph on S if each of the tasks T1, T2, T3,....T8 takes the same time and the system S has five processors?

• (a) 25%

• (b) 40%

• (c) 50%

• (d) 90%

Answer: (b) 40%. Read the graph as Start -> T1 -> T2; T2 forks into T3 -> T6, T4 -> T7, and T5 -> T8, then T6, T7, and T8 join at End. Let every task take one time unit.

1. Sequentially, tasks T1 through T8 require T_seq = 8 units.

2. The graph has four schedule levels: {T1}, {T2}, {T3,T4,T5}, and {T6,T7,T8}. Therefore T_parallel = 4 units, even with five processors.

3. Speedup is S = T_seq / T_parallel = 8 / 4 = 2.

4. Efficiency is E = S / 5 = 2 / 5 = 0.4 = 40%.

A second check gives the same result: useful work divided by available processor-time is 8 / (5 x 4) = 8 / 20 = 0.4. Dividing speedup by eight tasks would use the wrong denominator.

Tightly and loosely coupled multiprocessors: compare memory and communication

Question 9, written concept check

Differentiate between Tightly Coupled and Loosely Coupled multiprocessor systems based on memory sharing and communication mechanisms.

The deciding test is memory visibility. Shared addressing and synchronisation indicate tight coupling; private memory and messages indicate loose coupling.

Flynn's taxonomy concept check: classify a modern workload

Question 10, written concept check

Classify computer architectures using Flynn’s Taxonomy. Explain the fundamental differences between SIMD and MIMD architectures in terms of their processing logic and provide a practical example for each to demonstrate their utility in modern computing.

• SISD: one instruction stream operates on one data stream.

• SIMD: one instruction stream applies the same operation to several data elements.

• MISD: several instruction streams operate on the same data stream.

• MIMD: several independent instruction streams operate on several data streams.

SIMD broadcasts or issues the same operation across lanes, so it expresses data-level parallelism. Adding two arrays of 1,024 numbers uses the same addition at 1,024 element positions and suits GPU or vector lanes.

MIMD processors may execute different operations and control paths together, so task-level parallelism and coordination matter. A four-core server concurrently running a web request, a database query, a compression job, and a scheduler task is MIMD because the cores follow different instructions on different data. Multiple processing elements alone establish neither class; count the active instruction and data streams.

Multiprocessor classification MCQs: traps, revision route, and next step

Correct these five common traps:

• SIMD means many instructions. False. SIMD has one instruction stream across multiple data elements.

• More processors remove serial work. False. Amdahl's law leaves the serial portion unchanged.

• Five processors imply fivefold speedup. False. Precedence can leave processors idle.

• Parallel always means tightly coupled. Too broad outside the convention used by Question 5's options.

• A synchronous bus waits for an acknowledgement after every transfer. False. Predetermined clock slots distinguish it from asynchronous handshaking.

For response-format revision, use MCQ, MSQ or NAT? GATE Question Types Explained. For the next COA topic, continue with Floating Point Representation: IEEE 754 Format.

When you want structured Computer Architecture tests and broader mock practice, use the GATE Test Series. Keep the retrieval sequence short: streams -> coupling -> bus timing -> serial fraction -> precedence. The two numerical anchors are 20 + 80 / 4 = 40 seconds and 8 tasks / (5 processors x 4 time units) = 40% efficiency.