An instruction pipeline can be implemented by means of

Instruction pipelining relies on processing multiple instructions sequentially through different hardware stages simultaneously within a CPU. To maintain the correct order of execution while buffering data between these specific stages, a First-In-First-Out (FIFO) buffer is fundamentally required. LIFO buffers or stacks would reverse the order, which contradicts standard pipeline operation logic and data flow. Therefore, a FIFO buffer is the accurate choice for implementing an instruction pipeline effectively.