We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5…
2005
We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3 nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time How much time can be saved using design D2 over design D1 for executing 100 instructions?
Answer: B. 202 nsec — Key idea: the clock period for a synchronous pipeline is the maximum stage time; total time for N instructions = pipeline latency + (N − 1) × clock, where…
- A.
214 nsec
- B.
202 nsec
- C.
86 nsec
- D.
- 200 nsec
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Correct answer: B
Key idea: the clock period for a synchronous pipeline is the maximum stage time; total time for N instructions = pipeline latency + (N − 1) × clock, where latency = number of stages × clock.
Design D1:
Stage times: 3, 2, 4, 2, 3 nsec → clock = max = 4 nsec.
Pipeline latency = 5 × 4 = 20 nsec.
Total time for 100 instructions = 20 + 99 × 4 = 416 nsec.
Design D2:
8 stages, each 2 nsec → clock = 2 nsec.
Pipeline latency = 8 × 2 = 16 nsec.
Total time for 100 instructions = 16 + 99 × 2 = 214 nsec.
Time saved by using Design D2 over Design D1 = 416 − 214 = 202 nsec.
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