Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and…
2016
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is
Answer: A. 3.2 — First, calculate the execution time per instruction for the non-pipelined processor. Time = CPI / Clock Rate = 4 / (2.5 GHz) = 1.6 ns. Next, calculate the…
- A.
3.2
- B.
3.0
- C.
2.2
- D.
2.0
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Correct answer: A
First, calculate the execution time per instruction for the non-pipelined processor. Time = CPI / Clock Rate = 4 / (2.5 GHz) = 1.6 ns.
Next, calculate the execution time per instruction for the pipelined processor. With no stalls, CPI is approximately 1. Time = 1 / (2 GHz) = 0.5 ns.
Finally, calculate the speedup by dividing the non-pipelined time by the pipelined time: Speedup = 1.6 ns / 0.5 ns = 3.2.
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