A finite state machine (FSM) is implemented using the D flip-flops A and B,…
GATE · 2017 · EC · Set 1 · Electronics and Communication Engineering
A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are Q_AQ_B = 00, 01, 10, and 11. Assume that X_IN is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state Q_AQ_B = 00 and clocked, after a few clock cycles, it starts cycling through
- A.
all of the four possible states if X_IN = 1
- B.
three of the four possible states if X_IN = 0
- C.
only two of the four possible states if X_IN = 1
- D.
only two of the four possible states if X_IN = 0
Attempted by 10 students.
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