A 2-bit synchronous counter using two J-K flip flops is shown. The expressions…

GATE · 2018 · IN · Instrumentation Engineering

A 2-bit synchronous counter using two J-K flip flops is shown. The expressions for the inputs to the J-K flip flops are also shown in the figure. The output sequence of the counter starting from Q₁Q₂ = 00 is

Two edge-triggered J-K flip-flops form a synchronous counter. For Q₁: J₁ = Q₁ + Q₂ and K₁ = Q̄₁ + Q̄₂. For Q₂: J₂ = Q̄₁ + Q₂ and K₂ = Q₁ + Q̄₂. Both share the same clock.
  1. A.

    00 → 11 → 10 → 01 → 00 ···

  2. B.

    00 → 01 → 10 → 11 → 00 ···

  3. C.

    00 → 01 → 11 → 10 → 00 ···

  4. D.

    00 → 10 → 11 → 01 → 00 ···

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