The above circuit produces the output sequence, assuming the initial state of…

GATE · 1987 · CS · Question 1 subpartsModified — slightly modified from the official paper; see the solution

Four clocked JK flip-flops form a shift register. Each J input after the first is driven by the previous Q, and each K input by the previous complement Q. The first J receives the XOR of the third and fourth Q outputs; its K receives the inverse of that XOR. The fourth Q is the output.

The above circuit produces the output sequence, assuming the initial state of the four flip-flops is 1111 and taking the output before each clock edge:

  1. A.

    11111111000000001111\quad 1111\quad0000\quad0000

  2. B.

    11110000111100001111 \quad 0000\quad1111\quad0000

  3. C.

    11110001001101011111 \quad 0001\quad0011\quad0101

  4. D.

    10101010101010101010\quad1010\quad1010\quad1010

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