What does the circuit shown below represent?

2017

What does the circuit shown below represent?

Logic diagram. Input D feeds a transmission gate whose upper, plain control line is labelled CLK and whose lower, bubbled control line is labelled CLK-bar. The gate output node runs to the input of an inverter; that same node is also taken off to the right as the output Q, and the inverter output is labelled Q-bar. From the Q-bar node a wire runs down to the input of a second inverter, whose output feeds a second transmission gate. The second gate has a bubbled control labelled CLK and a plain control labelled CLK-bar, and its output returns to the node between the first transmission gate and the first inverter.

Answer: B. Positive level sensitive D-latch — Concept. A CMOS transmission gate conducts when its plain (n-channel) control is 1 while its bubbled (p-channel) control is 0. A clocked storage cell is…

  1. A.

    D flip-flop

  2. B.

    Positive level sensitive D-latch

  3. C.

    Negative level sensitive D-latch

  4. D.

    None of the above

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Correct answer: B

Concept. A CMOS transmission gate conducts when its plain (n-channel) control is 1 while its bubbled (p-channel) control is 0. A clocked storage cell is level-sensitive — a latch — when one clocked switch sits in the input path and a second, oppositely clocked switch closes an inverter feedback loop: that arrangement gives exactly one transparent window per clock period, and during it the output tracks the input continuously. The same cell is edge-triggered — a flip-flop — only when two such stages are cascaded on opposite clock phases, so data advances one stage per half-period and can reach the output only through the handover at a clock transition.

Application. Read the two transmission gates of the figure by their control labels:

  1. Input gate: plain control = CLK, bubbled control = CLK-bar, so it conducts while CLK = 1 and passes D to the internal node.

  2. That internal node is brought out as Q, and the inverter it drives produces Q-bar.

  3. Feedback gate: bubbled control = CLK, plain control = CLK-bar, so it conducts while CLK = 0 and returns the second inverter output to the same internal node.

  4. While CLK = 1 the input gate conducts and the feedback gate is open, so the cell is transparent and Q = D.

  5. While CLK = 0 the input gate is open and the feedback gate conducts, so the two inverters form a cross-coupled loop that holds the value present at the falling edge.

Cross-check. Test the structure against the alternatives:

  • Only one clocked stage lies between D and Q, so there is no master-slave handover: the output changes throughout the high phase, not only at an edge. That rules out edge-triggered operation.

  • The transparent window coincides with CLK = 1 and the hold window with CLK = 0, so the level sensitivity is positive, not negative.

  • A standard named structure does describe the cell, so the list of named structures is not exhausted.

Result. The circuit is a positive level-sensitive D-latch: transparent (Q = D) while CLK is high, and holding the stored value while CLK is low.

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