Match the following IC families with their basic circuits : List - I (IC…

Concept — A logic family is defined by the transistor arrangement in its input and output stages, and that arrangement fixes which gate is the family's natural building block - the cell it fabricates most compactly, and from which its remaining gates are then built. Switching devices in series combine inputs in an AND sense, devices in parallel combine them in an OR sense, and an inverting output stage converts either combination into NAND or NOR. A family whose elementary cell is a single complementary switching pair combines nothing at all; it performs inversion.

Applying this to each family

• TTL - the input device is a multi-emitter transistor whose emitters are driven by the inputs, so base drive reaches the phase splitter only when every input is high. That is an AND of the inputs, and the totem-pole output stage inverts it, so the elementary TTL cell is the NAND gate; TTL AND, OR, NOR and inverter parts are all derived from that cell.

• ECL - the core is a current-steering differential pair whose input transistors share a common emitter node. Any one input going high steers the current into that branch and pulls its collector down, so the coupled inputs perform an OR and the collector output inverts it. The elementary ECL cell is therefore the NOR gate, with the complementary OR available at the reference-side collector.

• CMOS - the elementary cell is one p-channel and one n-channel transistor in series between supply and ground with their gates tied together, so one of the two devices conducts at each input level. A single input leaves nothing to combine and the output is the complement of the input, so this cell is the inverter; CMOS NAND, NOR and complex gates are built by expanding it into series and parallel PMOS-NMOS networks.

Cross-check by contrast

• Pairing TTL with the inverter mistakes a derived part for the elementary cell: a TTL inverter is the same NAND cell built with a single-emitter input transistor.

• Pairing CMOS with NAND skips a level of construction: a CMOS NAND needs two series n-channel devices and two parallel p-channel devices, that is two complementary pairs rather than one.

• Pairing TTL with NOR confuses the two bipolar input mechanisms: TTL combines its inputs through one multi-emitter device, giving all-inputs AND behaviour, whereas the emitter-coupled OR-ing that yields NOR belongs to ECL.

Result — the code a-1, b-2, c-3 - TTL pairs with NAND, ECL with NOR, and CMOS with the inverter.