Q. A CPU with an 8 ns clock period requires 6 cycles for a memory reference, 4…
Q. A CPU with an 8 ns clock period requires 6 cycles for a memory reference, 4 cycles for an ALU operation, and 2 cycles for a register reference.The following program is stored in memory starting at address (4150)₁₀ and is executed sequentially:
Instruction | Meaning | Size (in Bytes) |
MOV D₀, @1000 | D₀ ← M[[1000]] | 8 |
MOV D₁, 7(D₀) | D₁ ← M[7 + [D₀]] | 6 |
ADD [7800], D₀ | M[7800] ← M[7800] + D₀ | 8 |
MUL D₁, @4500 | D₁ ← D₁ × M[[4500]] | 8 |
MOV 5(D₁), [1000] | M[5 + [D₁]] ← M[1000] | 6 |
HALT | — | 2 |
Assume the system supports word-addressable memory with a word size of 16 bits.
If no interrupt occurs, what is the total program execution time (in ns)?
Answer: B. 1584 ns — Approach: Count cycles per instruction by converting instruction size (in bytes) to words (word size = 16 bits = 2 bytes). Each memory reference (including…
- A.
1552 ns
- B.
1584 ns
- C.
1568 ns
- D.
1600 ns
Attempted by 16 students.
Show answer & explanation
Correct answer: B
Approach: Count cycles per instruction by converting instruction size (in bytes) to words (word size = 16 bits = 2 bytes). Each memory reference (including each instruction word fetch and each data read/write) costs 6 cycles, each ALU operation costs 4 cycles, and each register access costs 2 cycles. Clock period = 8 ns.
MOV D0, @1000 (8 bytes = 4 words): instruction fetch = 4 × 6 = 24 cycles; double-indirect data reads = 2 × 6 = 12 cycles; register write = 2 cycles. Total = 24 + 12 + 2 = 38 cycles.
MOV D1, 7(D0) (6 bytes = 3 words): instruction fetch = 3 × 6 = 18 cycles; register read = 2 cycles; address add (ALU) = 4 cycles; data read = 6 cycles; register write = 2 cycles. Total = 18 + 2 + 4 + 6 + 2 = 32 cycles.
ADD [7800], D0 (8 bytes = 4 words): instruction fetch = 4 × 6 = 24 cycles; data read = 6 cycles; register read = 2 cycles; ALU add = 4 cycles; data write = 6 cycles. Total = 24 + 6 + 2 + 4 + 6 = 42 cycles.
MUL D1, @4500 (8 bytes = 4 words): instruction fetch = 4 × 6 = 24 cycles; double-indirect data reads = 2 × 6 = 12 cycles; register read = 2 cycles; ALU multiply = 4 cycles; register write = 2 cycles. Total = 24 + 12 + 2 + 4 + 2 = 44 cycles.
MOV 5(D1), [1000] (6 bytes = 3 words): instruction fetch = 3 × 6 = 18 cycles; data read from [1000] = 6 cycles; register read = 2 cycles; address add (ALU) = 4 cycles; data write = 6 cycles. Total = 18 + 6 + 2 + 4 + 6 = 36 cycles.
HALT (2 bytes = 1 word): instruction fetch = 1 × 6 = 6 cycles. Total = 6 cycles.
Total cycles = 38 + 32 + 42 + 44 + 36 + 6 = 198 cycles.
Final execution time = 198 cycles × 8 ns = 1584 ns
A video solution is available for this question — log in and enroll to watch it.