Consider the following circuit involving a positive edge triggered D FF.…
2005
Consider the following circuit involving a positive edge triggered D FF.
Consider the following timing diagram. Let Ai represent the logic level on the line A in the i-th clock period.
Let A' represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is
Answer: A. A0 Al A1' A3 A4 — Key insight: the D flip-flop is positive-edge triggered, so at each rising clock edge the output Y takes the value present at the D input immediately before…
- A.
A0 Al A1' A3 A4
- B.
A0 Al A2' A3 A4
- C.
Al A2 A2' A3 A4
- D.
Al A2' A3 A4 A5'
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Correct answer: A
Key insight: the D flip-flop is positive-edge triggered, so at each rising clock edge the output Y takes the value present at the D input immediately before that edge.
Step-by-step evaluation of what D is at each rising edge (edges that start periods 1 through 5):
At the rising edge that begins period 1 the D input equals A0, so Y becomes A0.
At the rising edge that begins period 2 the D input equals A1, so Y becomes A1.
At the rising edge that begins period 3 the combinational path feeding D evaluates to the complement of the value A had in period 1 (that is, A1'), so Y becomes A1'.
At the rising edge that begins period 4 the D input equals A3, so Y becomes A3.
At the rising edge that begins period 5 the D input equals A4, so Y becomes A4.
Final answer: the output sequence on Y over clock periods 1 through 5 is A0, A1, A1', A3, A4.
Tip: when solving similar problems, write down the value present on the D input immediately before each rising edge (use the timing diagram). That value is what the flip-flop will output after the edge.
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