Consider the following circuit involving three D-type flip-flops used in a…
2011
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.
If at some instance prior to the occurrence of the clock edge, P,Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
Answer: D. 011 — In the given circuit, the D inputs of the flip-flops are driven by the inverted feedback through the logic gates, which makes the outputs toggle according to…
- A.
000
- B.
001
- C.
010
- D.
011
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Correct answer: D
In the given circuit, the D inputs of the flip-flops are driven by the inverted feedback through the logic gates, which makes the outputs toggle according to a Gray-code style pattern. After analyzing the next-state equations, we get:
Pnext=P'
Qnext=P⊕Q
Rnext=R⊕(P⋅Q)
Starting from the initial state 000, the first valid next state generated by the circuit is:
P=0→1,Q=0→1,R=0→1
So the first stable output becomes:
Hence, the correct answer is 011.
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