We consider the addition of two 2’s complement numbers bn-1bn-2...b0 and…

Concept: For an n-bit two’s-complement adder built from a plain unsigned binary adder, overflow occurs precisely when the two operand sign bits agree with each other but the sign bit of the sum comes out different from them — equivalently, when the carry generated into the most-significant bit differs from the carry generated out of it.

1. Let an-1 and bn-1 be the sign (MSB) bits of the two operands, and let cn-1 be the sign (MSB) bit of the sum, exactly as the question defines them.

2. Overflow happens in exactly two cases: both operands are non-negative (an-1 = 0, bn-1 = 0) yet the sum's sign bit comes out 1; or both operands are negative (an-1 = 1, bn-1 = 1) yet the sum's sign bit comes out 0.

3. Writing these two cases as a Boolean sum of products gives an-1 · bn-1 · (NOT cn-1) + (NOT an-1) · (NOT bn-1) · cn-1 — an expression built only from an-1, bn-1 and cn-1 in this same-sign / different-result-sign form.

Cross-check with numbers (4-bit register):

• Adding 0111 (+7) and 0111 (+7): the unsigned sum is 1110 with no carry out of the register. Both operand sign bits are 0 and the sum's sign bit is 1, so the expression above evaluates to 1 — correctly, since 7+7=14 cannot be represented in 4-bit two's complement.

• Adding 1000 (−8) and 1000 (−8): the unsigned sum is 0000 with a carry out of the register. Both operand sign bits are 1 and the sum's sign bit is 0, so the expression again evaluates to 1 — correctly, since −8+−8=−16 is out of the representable range.

• Adding operands of opposite sign, e.g. 0100 (+4) and 1011 (−5), can never overflow by definition; here an-1 and bn-1 are not equal, so both product terms of the expression are 0 and it correctly evaluates to 0.

So the option built from an-1, bn-1 and cn-1 in this “same operand signs, different result sign” form is the correctly identified overflow condition.