Which 8085 input signal is used to interface a slow memory device by inserting…

Concept

A processor bus cycle has fixed timing, while a memory device may need longer to produce or accept data. A readiness handshake lets the processor extend the current machine cycle with wait states until the device can safely complete the transfer.

Application

For an 8085 memory access, the addressed slow device or its interface logic keeps READY low while its data is not available. The processor inserts wait states and resumes the same machine cycle when READY becomes high.

Contrast

• INTR requests maskable interrupt service; it does not extend an active memory bus cycle.

• RESET IN initializes the processor and resets its execution state.

• HOLD asks the processor to release the system buses to another bus master, such as a DMA controller.

• READY controls whether the current machine cycle proceeds or is extended by wait states.

Cross-check

If READY is low, the 8085 remains in wait states; when READY returns high, the pending transfer continues. This behavior directly matches the timing need of a slow memory device.

Result

The signal required to interface the slow memory device is READY.