A processor fetches instructions at a rate of 1 MIPS. A DMA module transfers…

Concept

In cycle-stealing DMA, the processor pauses for one memory cycle whenever the DMA controller transfers one data unit. When an instruction fetch and a DMA transfer occupy equal-duration memory cycles, processor time lost per second equals DMA transfers per second multiplied by the duration of one instruction-fetch cycle.

Application

1. Convert the device rate to characters per second: 9600 bits/s ÷ 8 bits/character = 1200 characters/s.

2. With one stolen memory cycle per character, DMA takes 1200 processor cycles during each second.

3. At 1 MIPS, one million instruction fetches take one second. Under the stated equal-cycle assumption, one memory cycle therefore takes 1 microsecond.

4. The total stolen time is 1200 × 1 microsecond = 1200 microseconds = 1.2 ms per second.

Cross-check

The stolen fraction is 1200 ÷ 1,000,000 = 0.0012 = 0.12%. Taking 0.12% of one second again gives 0.0012 s = 1.2 ms.

Therefore, the processor loses 1.2 ms of execution time during each second of operation.