The ability to temporarily halt the CPU and use this time to send information…
2008
The ability to temporarily halt the CPU and use this time to send information on buses is called
Answer: D. cycle stealing — The correct concept is Cycle Stealing. In this process, the DMA controller temporarily halts CPU execution to gain control of system buses for data transfer.…
- A.
direct memory access
- B.
vectoring the interrupt
- C.
polling
- D.
cycle stealing
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Correct answer: D
The correct concept is Cycle Stealing. In this process, the DMA controller temporarily halts CPU execution to gain control of system buses for data transfer. This allows information to be sent on the buses without requiring constant CPU involvement, distinguishing it from general Direct Memory Access.
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