Consider a 33 MHz CPU based system. What is the number of wait states required…

Concept: When a CPU's clock cycle is shorter than the time a memory device needs to respond, the memory interface must insert idle clock cycles — wait states — so the total elapsed time covers the memory's actual response time. If T is the CPU clock period and A is the total time the interface needs (raw memory access time plus any buffering/decoding delay), the number of whole clock cycles required is N = ceil(A / T). Because the first of those cycles is the base memory-access cycle itself, the number of wait states inserted equals (N − 1), not N.

Applying this to the given system:

1. Clock period: T = 1 / f = 1 / 33 MHz ≈ 30.3 ns.

2. Total time the interface needs: A = memory access time + circuitry delay = 60 ns + 10 ns = 70 ns.

3. Clock cycles required: N = ceil(A / T) = ceil(70 / 30.3) = ceil(2.31) = 3 cycles.

4. Wait states = N − 1 = 3 − 1 = 2.

Cross-check: With 2 wait states (3 total cycles), the interface allows 3 × 30.3 ns ≈ 90.9 ns — enough to cover the 70 ns requirement. With only 1 wait state (2 total cycles), it allows just 2 × 30.3 ns ≈ 60.6 ns, short of the 70 ns needed. So 2 wait states is the minimum count that satisfies the timing requirement, confirming the value obtained above. (Note: rounding 70/30.3 up to 3 gives the TOTAL number of clock cycles needed — the wait states are the cycles ADDED to the base cycle, i.e. 3 − 1 = 2, not 3.)