The above synchronous sequential circuit built using JK flip-flops is…
GATE · 2014 · CS · Set 3 · Computer Science & IT
The above synchronous sequential circuit built using JK flip-flops is initialized with . The state sequence for this circuit for the next 3 clock cycles is
- A.
001, 010, 011
- B.
111, 110, 101
- C.
100, 110, 111
- D.
100, 011, 001
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