The instruction pipeline of a RISC processor has the following stages:…
2018
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.
The number of clock cycles required for completion of execution of the sequence of instructions is ______.
Answer: 219 — Key idea: the perform-operation stage is multi-cycle and becomes the throughput bottleneck. The pipeline requires the initial decode/fetch stages before the…
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Correct answer: 219
Key idea: the perform-operation stage is multi-cycle and becomes the throughput bottleneck. The pipeline requires the initial decode/fetch stages before the first perform-operation and a final writeback after the last perform-operation, so total cycles = 3 (IF+ID+OF) + sum of all perform-operation cycles + 1 (final WB).
Compute total perform-operation cycles: 40 instructions × 3 cycles + 35 instructions × 2 cycles + 25 instructions × 1 cycle = 120 + 70 + 25 = 215 cycles.
Total clock cycles = 3 (IF+ID+OF) + 215 (all PO cycles) + 1 (final WB) = 219 cycles.
Final answer: 219 clock cycles.
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