Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and…
2015
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is_________.
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Correct answer: 3.2
Given: Non-pipelined clock = 2.5 GHz, average cycles per instruction = 4; Pipelined clock = 2.0 GHz, pipeline depth = 5 stages, assume no stalls so ideal cycles per instruction = 1.
Non-pipelined time per instruction = cycles / clock = 4 / 2.5 GHz = 4 / 2.5e9 s = 1.6e-9 s = 1.6 ns.
Pipelined time per instruction (ideal) = 1 / 2.0 GHz = 1 / 2e9 s = 0.5e-9 s = 0.5 ns.
Speedup: Speedup = (non-pipelined time) / (pipelined time) = (4 / 2.5 GHz) / (1 / 2.0 GHz) = (4 / 2.5) × (2.0 / 1) = 1.6 × 2 = 3.2.
Therefore the achieved speedup is 3.2.
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