Consider a pipelined processor with 5 stages, Instruction Fetch(IF),…
2021
Consider a pipelined processor with 5 stages, Instruction Fetch(IF), Instruction Decode(ID), Execute (EX),Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. Assume that the ID stage merely decodes the instruction and the register read is performed in the EX stage. The EX stage takes one cycle for ADD instruction and the register read is performed in the EX stage, The EX stage takes one cycle for ADD instruction and two cycles for MUL instruction. Ignore pipeline register latencies.
Consider the following sequence of 8 instructions:
\(\textsf{ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL}\)
Assume that every MUL instruction is data-dependent on the ADD instruction just before it and every ADD instruction (except the first ADD) is data-dependent on the MUL instruction just before it. The speedup defined as follows.
\(\textit{Speedup} = \dfrac{\text{Execution time without operand forwarding}}{\text{Execution time with operand forearding}}\)
The \(Speedup \) achieved in executing the given instruction sequence on the pipelined processor (rounded to 2 decimal places) is _____________ .
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Correct answer: 1.87 to 1.88
Pipeline stages: IF(1), ID(1), EX(variable), MEM(1), WB(1).
EX times: ADD = 1, MUL = 2. Instruction sequence:
I1:ADD, I2:MUL, I3:ADD, I4:MUL, I5:ADD, I6:MUL, I7:ADD, I8:MUL
Each MUL depends on previous ADD; each ADD (except I1) depends on previous MUL.
1) Without operand forwarding
A consumer must wait till producer’s WB completes before starting its EX (register read happens in EX). Scheduling yields:
I1 WB at cycle 5
I2 EX starts at cycle 6 → WB at 9
I3 EX starts at 10 → WB at 12
I4 WB at 16
I5 WB at 19
I6 WB at 23
I7 WB at 26
I8 WB at 30
Total cycles = 30.
2) With operand forwarding (PO→OF allowed)
A consumer can start EX one cycle after producer’s EX finishes (no need to wait for WB). Scheduling yields:
I1 EX ends at 3 → I2 EX starts 4, I2 EX ends 5
I3 EX starts 6, ends 6
I4 EX starts 7, ends 8
I5 EX starts 9, ends 9
I6 EX starts 10, ends 11
I7 EX starts 12, ends 12
I8 EX starts 13, ends 14 → final WB at 16
Total cycles = 16.
Speedup = 30 / 16 = 1.875 ≈ 1.87 (rounded to two decimals).
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