Instruction execution in a processor is divided into 5 stages, Instruction…
2017
Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementation of the processor are contemplated:
I. a naive pipeline implementation (NP) with 5 stages and
II. an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.
The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is _________ .
Attempted by 90 students.
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Correct answer: 1.51
Key idea: the pipelined clock cycle equals the largest stage delay plus the buffer (register) delay; total time to execute n instructions on a k-stage pipeline is (k + n - 1) × cycle_time.
Given stage times (ns): IF = 5, ID = 4, OF = 20 (split in the efficient design into OF1 = 12 and OF2 = 8), EX = 10, WB = 3. Buffer (register) delay = 2 ns. Number of instructions n = 20.
Naive pipeline (5 stages): stage delays = 5, 4, 20, 10, 3. Maximum stage delay = 20 ns. Cycle time = 20 + 2 = 22 ns. Pipeline depth k = 5.
Efficient pipeline (OF split into OF1 and OF2 → 6 stages): stage delays = 5, 4, 12, 8, 10, 3. Maximum stage delay = 12 ns. Cycle time = 12 + 2 = 14 ns. Pipeline depth k = 6.
Total execution time formula for n instructions: (k + n - 1) × cycle_time.
Compute total times:
Naive pipeline time = (5 + 20 - 1) × 22 = 24 × 22 = 528 ns.
Efficient pipeline time = (6 + 20 - 1) × 14 = 25 × 14 = 350 ns.
Speedup of the efficient pipeline over the naive pipeline = naive_time / efficient_time = 528 / 350 ≈ 1.51 (rounded to two decimal places).
Answer: 1.51
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