Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock…
2020
Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. A 5-stage pipeline is made from this processor. Pipelining overhead forces the pipelined processor to operate at 2 GHz. In a given program, 30% of the instructions are memory instructions, 60% are ALU instructions, and the remaining instructions are branch instructions. Cache misses cause 5% of the memory instructions to stall for 50 clock cycles each, and 50% of the branch instructions stall for 2 cycles each. Assume that ALU instructions cause no stalls. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is __________.
Answer: 2.15 to 2.18 — ConceptProcessor speedup is the execution time before an improvement divided by the execution time after the improvement. For a long instruction stream,…
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Correct answer: 2.15 to 2.18
Concept
Processor speedup is the execution time before an improvement divided by the execution time after the improvement. For a long instruction stream, average execution time per instruction equals average CPI multiplied by the clock period.
A non-pipelined processor uses its stated CPI directly. An ideal pipeline has steady-state CPI 1; the average stall cycles per instruction are added to this ideal CPI.
Application
The non-pipelined clock period is 1 / 2.5 GHz = 0.4 ns. Its CPI is 5, so its average time per instruction is 5 × 0.4 = 2 ns.
Branch instructions form the remaining fraction: 1 − 0.30 − 0.60 = 0.10.
The average memory-stall contribution in the pipeline is 0.30 × 0.05 × 50 = 0.75 cycle per instruction.
The average branch-stall contribution in the pipeline is 0.10 × 0.50 × 2 = 0.10 cycle per instruction.
Therefore, the pipelined average CPI is 1 + 0.75 + 0.10 = 1.85.
The pipelined clock period is 1 / 2 GHz = 0.5 ns, so its average time per instruction is 1.85 × 0.5 = 0.925 ns.
Speedup = 2 / 0.925 = 2.162162...; rounded to two decimal places, this is 2.16.
Cross-check
The official GATE 2020 CS final key accepts the range 2.15 to 2.18 for this NAT item, and the computed value 2.16 lies in that range. Stall penalties are applied to the pipelined design because the question introduces them while describing the program executed on that design; adding them again to the original processor would incorrectly change its stated five-cycle instruction time.
Result
The speedup is 2.16, with the official accepted range 2.15 to 2.18.