Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock…

Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. A 5-stage pipeline is made from this processor. Pipelining overhead forces the pipelined processor to operate at 2 GHz. In a given program, 30% of the instructions are memory instructions, 60% are ALU instructions, and the remaining instructions are branch instructions. Cache misses cause 5% of the memory instructions to stall for 50 clock cycles each, and 50% of the branch instructions stall for 2 cycles each. Assume that ALU instructions cause no stalls. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is __________.