A computer system has a level-1 instruction cache (1-cache), a level-1 data…
2006
A computer system has a level-1 instruction cache (1-cache), a level-1 data cache (D-cache) and a level-2 cache (L2-cache) with the following specifications:
The length of the physical address of a word in the main memory is 30 bits. The capacity of the tag memory in the I-cache, D-cache and L2-cache is, respectively,
Answer: A. 1 K x 18-bit, 1 K x 19-bit, 4 K x 16-bit — Answer: Key idea: tag bits = physical address bits - index bits - block-offset bits. The physical address given is a word address of 30 bits. I-cache (4K…
- A.
1 K x 18-bit, 1 K x 19-bit, 4 K x 16-bit
- B.
1 K x 16-bit, 1 K x 19-bit, 4 K x 18-bit
- C.
1 K x 16-bit, 512 x 18-bit, 1 K x 16-bit
- D.
1 K x 18-bit, 512 x 18-bit, 1 K x 18-bit
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Correct answer: A
Answer:
Key idea: tag bits = physical address bits - index bits - block-offset bits. The physical address given is a word address of 30 bits.
I-cache (4K words, direct mapped, block = 4 words):
Number of lines = 4K / 4 = 1K ⇒ index = log2(1K) = 10 bits. Block offset = log2(4) = 2 bits. Tag = 30 - 10 - 2 = 18 bits. Tag memory = 1K × 18-bit.
D-cache (4K words, 2-way set-associative, block = 4 words):
Total blocks = 4K / 4 = 1K. With 2-way, sets = 1K / 2 = 512 ⇒ index = log2(512) = 9 bits. Block offset = 2 bits. Tag = 30 - 9 - 2 = 19 bits. Number of tag entries = total blocks = 1K ⇒ tag memory = 1K × 19-bit.
L2-cache (64K words, 4-way set-associative, block = 16 words):
Total blocks = 64K / 16 = 4K. With 4-way, sets = 4K / 4 = 1K ⇒ index = log2(1K) = 10 bits. Block offset = log2(16) = 4 bits. Tag = 30 - 10 - 4 = 16 bits. Number of tag entries = total blocks = 4K ⇒ tag memory = 4K × 16-bit.
Therefore, the tag memory capacities are: 1K × 18-bit, 1K × 19-bit, 4K × 16-bit.
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