Consider two cache organizations: The first one is 32 KB 2-way set associative…

Concept — the hit latency of a cache lookup is the delay of the tag-comparison path plus any extra stage needed to steer the selected data out. A direct-mapped cache compares a single tag and needs no such stage, while an n-way set-associative cache compares its n tags at the same time and then needs an n-to-1 multiplexer to pass the matching way through. The comparator width follows from the address split: block offset = log2(block size), index = log2(number of sets), tag = address width − index − offset, where number of sets = (cache size ÷ block size) ÷ associativity.

Applying this to the 2-way set-associative organization

1. Total blocks = 32 KB ÷ 32 B = 32768 ÷ 32 = 1024 blocks.

2. Associativity is 2, so number of sets = 1024 ÷ 2 = 512, giving index = log2 512 = 9 bits.

3. Block size is 32 B, so block offset = log2 32 = 5 bits.

4. Tag = address width − index − offset = 32 − 9 − 5 = 18 bits.

5. A k-bit comparator costs k/10 ns, so the 18-bit comparator costs 18/10 = 1.8 ns. Both ways are compared at the same time, so this delay is paid once and not twice.

6. Passing the matching way through needs one 2-to-1 multiplexer, which costs 0.6 ns.

7. Hit latency of the set-associative organization: h1 = 1.8 + 0.6 = 2.4 ns.

Cross-check — the direct-mapped organization of the same size: with 1024 blocks and no associativity there are 1024 sets, so index = log2 1024 = 10 bits, the offset is still 5 bits, and tag = 32 − 10 − 5 = 17 bits. Its comparator costs 17/10 = 1.7 ns and no way-selection multiplexer is required, so h2 = 1.7 ns. The 0.7 ns gap between the two organizations is exactly one extra tag bit (0.1 ns) plus the multiplexer (0.6 ns), which confirms the arithmetic above.