ISRO CS Computer Organization and Architecture PYQs: 7 Solved Questions

Computer Organization and Architecture questions in ISRO CS are often decided by one small conversion: bytes per word, blocks per set, clock period, an interrupt vector or the location of an operand.

Below are seven exact ISRO previous-year questions with their original options, correct answers and worked explanations.

For the complete preparation route, use the ISRO Scientist/Engineer SC Computer Science course and the ISRO preparation hub.

The six checks that solve most ISRO COA questions

• Cache mapping: convert words to bytes before finding offset, line or set bits.

• Address lines: take the ceiling of log₂ of the number of byte locations.

• Wait states: first find total clock cycles, then subtract the base access cycle.

• Interrupts: distinguish fixed vector addresses from mask priority.

• Control units: a microprogram is a sequence of microinstructions, not machine code.

• Addressing modes: immediate mode stores the operand inside the instruction.

1. Direct-mapped cache block — ISRO CS 2011

Question

Consider a direct-mapped cache with 64 blocks and a block size of 16 bytes. To which cache block does byte address 1206 map?

• (A) It does not map

• (B) 6

• (C) 11

• (D) 54

Correct answer: (C) 11

Explanation

First find the main-memory block number. Byte address 1206 lies in block floor(1206/16) = 75, with byte offset 6 inside that block.

For a direct-mapped cache, cache line = memory block number mod number of cache lines. Therefore, 75 mod 64 = 11. The byte offset does not choose the cache line; it chooses the byte after the block has been placed.

2. Two-way set-associative address fields — ISRO CS 2017

Question

A two way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The physical address space is 4 GB. The number of bits in the TAG, SET fields are

• (A) 20, 7

• (B) 19, 8

• (C) 20, 8

• (D) 21, 9

Correct answer: (B) 19, 8

Explanation

A 32-bit word is 4 bytes, so an 8-word block is 32 bytes = 2⁵ bytes. Hence the block offset needs 5 bits.

The 16 KB cache contains 2¹⁴/2⁵ = 2⁹ cache lines. Because it is two-way set associative, the number of sets is 2⁹/2 = 2⁸, so the set field needs 8 bits. A 4 GB byte-addressable space uses 32-bit addresses, leaving 32 - 8 - 5 = 19 tag bits.

3. Address lines for a RAM-chip array — ISRO CS 2014

Question

If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 × 6 array, where each chip is 8K × 4 bits?

• (A) 13

• (B) 15

• (C) 16

• (D) 17

Correct answer: (D) 17

Explanation

There are 4 × 6 = 24 chips. Each chip stores 8K × 4 bits = 32K bits = 4 KB. Therefore, total capacity is 24 × 4 KB = 96 KB, or 98,304 byte locations.

Sixteen address lines cover only 2¹⁶ = 65,536 locations. Seventeen lines cover up to 2¹⁷ = 131,072 locations. Since the required count lies between them, the system needs 17 address lines.

4. Memory-interface wait states — ISRO CS 2014

Question

Consider a 33 MHz CPU based system. What is the number of wait states required if it is interfaced with a 60 ns memory? Assume a maximum of 10 ns delay for additional circuitry like buffering and decoding.

• (A) 0

• (B) 1

• (C) 2

• (D) 3

Correct answer: (C) 2

Explanation

The CPU clock period is 1/33 MHz ≈ 30.3 ns. The complete memory path needs 60 ns + 10 ns = 70 ns.

The required number of clock cycles is ceil(70/30.3) = ceil(2.31) = 3 cycles. One is the normal access cycle, so the number of extra wait states is 3 - 1 = 2. A frequent mistake is reporting three, which is the total cycle count rather than the inserted waits.

5. 8085 TRAP interrupt vector — ISRO CS 2013

Question

In 8085 microprocessor, the ISR for handling trap interrupt is at which location?

• (A) 3CH

• (B) 34H

• (C) 74H

• (D) 24H

Correct answer: (D) 24H

Explanation

TRAP is the highest-priority, non-maskable vectored interrupt in the 8085. Its fixed vector address is 0024H. When TRAP is accepted, execution transfers to the interrupt service routine beginning at that location.

The key is to recall the vector table, not to derive the address from interrupt priority. Priority tells which request is served first; the vector tells where its service routine begins.

6. Meaning of a microprogram — ISRO CS 2018

Question

Micro program is

• (A) the name of a source program in micro computers

• (B) set of micro instructions that defines the individual operations in response to a machine-language instruction

• (C) a primitive form of macros used in assembly language programming

• (D) a very small segment of machine code

Correct answer: (B) Set of micro instructions that defines the individual operations in response to a machine-language instruction

Explanation

In a microprogrammed control unit, each machine instruction is realised through an ordered sequence of microinstructions stored in control memory. Those microinstructions generate the detailed control signals needed for register transfers, ALU actions and memory operations.

A microprogram is therefore below the assembly and machine-instruction level. It is not a source program, an assembly macro or merely a short piece of machine code.

7. Immediate addressing mode — ISRO CS 2020

Question

The immediate addressing mode can be used for:

1. Loading internal registers with initial values.

2. Performing arithmetic or logical operation on data contained in instructions.

Which of the following is true?

• (A) Only 1

• (B) Only 2

• (C) Both 1 and 2

• (D) Neither 1 nor 2

Correct answer: (C) Both 1 and 2

Explanation

In immediate addressing, the operand value is encoded directly inside the instruction. A processor can therefore load a constant into a register and can also apply an arithmetic or logical operation to an immediate constant.

For example, instructions conceptually written as MOV R1, #10 and ADD R1, #5 use immediate data. No separate memory access is needed to fetch those operand values, so both statements are correct.

Common traps in these ISRO COA PYQs

For more exact ISRO practice, continue with the ISRO CS DBMS solved PYQs and the ISRO CS Operating Systems PYQ guide.

A 15-minute revision loop

Attempt all seven questions again without reading the explanations. For every wrong answer, write one line only: block before modulo, lines divided by ways, ceil for address lines, total cycles minus one, TRAP equals 0024H, microprogram equals microinstructions, or immediate equals operand inside instruction.

Then solve the options once more. These compact rules are more reusable under exam pressure than memorising an isolated option letter.