Consider a 2-way word addressable set associative cache with a block size of…
Consider a 2-way word addressable set associative cache with a block size of 16 words and cache size is 256 KBytes. If each word is 32 bits and physical address is 28 bits, how many of the physical address bits are used as TAG bits?
Answer: B. 13 — Explanation: Memory is word addressable and a cache block size is 16 words meaning 4 offset bits. Cache size = 256KB Each word size is 32 bits = 4 bytes.…
- A.
10
- B.
13
- C.
24
- D.
48
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Correct answer: B
Explanation:
Memory is word addressable and a cache block size is 16 words meaning 4 offset bits.
Cache size = 256KB
Each word size is 32 bits = 4 bytes.
Cache size in words = 256KB/4 = 64K words
Each block is 16 words, number of blocks in the cache = 64K/ 16 = 4K
It is a 2-way set associative cache, number of sets in the cache = 4K/2 = 2K, we need 11 bits for the SET number.
Out of the 28 bits of physical address, TAG bits = 28 - 11 - 4 = 13