The main difference(s) between a CISC and a RISC processor is/are that a RISC…

1999

The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically:

  • a) has fewer instructions

  • b) has fewer addressing modes

  • c) has more registers

  • d) is easier to implement using hardwired control logic

Answer: D. a, b, c and dRISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) are two competing processor-design philosophies. RISC favours a small,…

  1. A.

    a and b

  2. B.

    b and c

  3. C.

    a and d

  4. D.

    a, b, c and d

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Correct answer: D

RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) are two competing processor-design philosophies. RISC favours a small, regular, fixed-format instruction set so that decoding and execution can be wired directly into hardware, whereas CISC uses richer, variable-length instructions — often relying on microcode — to pack more work into a single instruction.

Checking each of the four listed properties for a typical RISC processor against this principle:

  • a) has fewer instructions: RISC deliberately keeps the instruction repertoire small so each instruction is quick to decode and execute.

  • b) has fewer addressing modes: RISC typically follows a load-store design — only load/store instructions touch memory, and most other operations use simple register addressing.

  • c) has more registers: since operations work mainly on registers rather than memory, RISC needs a larger register file to hold live values and reduce memory traffic.

  • d) is easier to implement using hardwired control logic: simple, uniform, fixed-length instructions let the control unit be wired directly in hardware instead of relying on microprogramming, which speeds up execution.

None of these four traits contradicts the RISC design philosophy — each is a standard, well-documented distinction from CISC. Since all four hold together, the complete and correct combination is "a, b, c and d".

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