A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of…

Concept

A memory array is expanded in two independent directions: chips placed in parallel increase the word width, while banks selected by address decoding increase the number of addressable words.

A 2-to-4 decoder with an enable input can be cascaded: one decoder handles the two most-significant bank bits and enables one of four lower decoders, which together generate 16 bank-select lines.

Application

1. Width expansion: each chip supplies 8 bits per word, so two 1K × 8 chips in parallel form one 1K × 16 bank.

2. Depth expansion: 16K ÷ 1K = 16 banks are required, so four extra address bits must select one bank.

3. Decoder construction: one 2-to-4 decoder decodes the upper two bank-select bits. Its four outputs enable four lower 2-to-4 decoders, and those lower decoders generate 4 × 4 = 16 bank-select lines.

4. Total decoder count: 1 decoder at the first level + 4 decoders at the second level = 5 decoders.

Cross-check

The 16 bank-select lines choose exactly one of the sixteen 1K × 16 banks. Within the selected bank, the chip’s ten address inputs choose one of 1024 words, giving 16 × 1024 = 16K addressable words.

Result

Therefore, the required number of 2 × 4 decoders with enable line is 5.