The figure shows a digital circuit constructed using negative edge triggered…

Concept

A negative-edge-triggered JK flip-flop with J=K=1 toggles on every falling clock edge; with J and K unequal, its next state follows the standard JK excitation rule (J=1,K=0 -> Q=1; J=0,K=1 -> Q=0; J=K=0 -> Q holds). When a later stage's clock input is driven by an earlier flip-flop's output (instead of the master CLK directly), that stage updates only when its own clock signal makes the qualifying (here, falling) transition -- and its J/K must be evaluated using the state that existed just BEFORE that transition, not after. Tracing a full cycle therefore means stepping through the circuit edge by edge, not assuming a plain binary count.

Given:

• All flip-flops are negative edge triggered JK flip-flops

• Initial state:
  Q2Q1Q0 = 000
  

Step-by-Step State Transition

Flip-Flop Inputs

FF0
J0 = K0 = 1

So (Q0) toggles on every negative edge of CLK.

FF1

• Clock = Q0

• K1=1

• J1=(Q2)'

FF1 changes only when Q0 goes from 1 → 0.

FF2

• Clock = Q0

• K2=1

• J2=Q1

FF2 also changes only when Q0 goes from 1 → 0.

State Table

Cross-Check

Since FF1 and FF2 only respond to Q0's falling transition (every alternate CLK edge), the reachable states are restricted by the feedback J1=Q2′ and J2=Q1. The traced sequence 000→001→010→011→100→101→000 visits exactly 6 distinct states and never reaches 110 or 111 -- confirming this is a MOD-6 counter, not the MOD-8 count a plain 3-bit ripple counter (all J=K=1) would give.

Observation

After 6 clock cycles, the circuit returns to:
000

So the sequence repeats.

The state Q2Q1Q0 = 000 repeats after 6 clock cycles of CLK.