The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an…

Concept — what sets the ceiling on a programmed I/O transfer

In programmed I/O the processor itself is the data mover. For every unit of data the CPU must run a polling sequence — read the device status register, test the ready bit, branch on the result, and then execute the instruction that actually moves the datum. Nothing crosses the interface unless the CPU executes instructions for it. The maximum transfer rate is therefore the processor’s instruction throughput divided by the number of instructions each transferred byte costs.

Under DMA the ceiling is set by a different quantity — the memory-bus bandwidth the CPU leaves unused — because there a controller moves the data without CPU instructions. Recognising which of the two constraints binds is the skill this item tests.

What the stem fixes, and what the standard model supplies: the stem gives the instruction rate (1 MIPS) and the average number of machine cycles per instruction (4), but it does not spell out how many instructions one transferred byte of programmed I/O costs. The standard programmed I/O cost model — the one the official answer key applies to this item — charges each byte the four steps of the polling loop: input the status, check the status, branch on it, and read/write the data. That assumption is not derivable from the stem alone, so it is stated here openly; it is what turns the supplied figures into a single number.

Application to this system

1. Instruction throughput: the CPU executes at 1 MIPS = 1,000,000 instructions per second.

2. Machine-cycle rate: each instruction averages 4 machine cycles, so the machine runs 1,000,000 × 4 = 4,000,000 machine cycles per second.

3. Cost of one byte, on the stated model: four instructions per transferred byte — input the status, check the status, branch on it, then read/write the data, that last step being the one-machine-cycle memory read/write the stem mentions.

4. Machine cycles per byte: 4 instructions/byte × 4 machine cycles/instruction = 16 machine cycles per byte.

5. Maximum rate: 1,000,000 instructions per second ÷ 4 instructions per byte = 250,000 bytes per second. The same figure via cycles: 4,000,000 machine cycles per second ÷ 16 machine cycles per byte = 250,000 bytes per second.

6. Expressed in the units of the choices: 250,000 bytes per second = 250 Kbytes/sec.

Cross-check — where the 50% and the 90% figures belong

Those two numbers describe the memory bus, and they bound the companion DMA calculation rather than this one:

• Background programs take 90% of the CPU time and half of all machine cycles use the memory bus, so the programs consume 4,000,000 × 0.90 × 0.50 = 1,800,000 bus accesses per second.

• A memory read/write occupies exactly one machine cycle, and the 50% figure describes how often the CPU’s own cycles need the bus rather than a cap on the bus itself, so the bus could in principle be driven in every one of the 4,000,000 machine cycles per second. The spare capacity is therefore 4,000,000 − 1,800,000 = 2,200,000 accesses per second, i.e. 2.2 Mbytes/sec.

• That spare bandwidth is what a DMA controller could exploit. It is far more than a CPU-driven polling loop can consume, which confirms that instruction throughput — not memory-bus bandwidth — is the binding constraint for programmed I/O here.

Reading the four rates against the same yardstick

Result

The maximum I/O data transfer rate under programmed I/O is 250 Kbytes/sec: the four-instructions-per-byte polling cost applied to a 1 MIPS processor. This matches the official UGC NET June 2015 Computer Science (Paper III) final answer key for this item.