A DMA controller transfers 32-bit words to memory using cycle stealing. The…
2015
A DMA controller transfers 32-bit words to memory using cycle stealing. The words are assembled from a device transmitting 8-bit characters at 4,800 characters per second. The CPU fetches and executes instructions at an average rate of 1,000,000 instructions per second. Assume each 32-bit DMA word transfer steals one CPU bus cycle and that each stolen bus cycle delays the CPU by one instruction-time. By what percentage is the CPU slowed by the DMA transfer?
Answer: B. 0.12% — ConceptIn cycle stealing, DMA temporarily takes a memory-bus cycle from the CPU. When one stolen bus cycle displaces one instruction-time, the slowdown…
- A.
0.06%
- B.
0.12%
- C.
1.2%
- D.
2.5%
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Correct answer: B
Concept
In cycle stealing, DMA temporarily takes a memory-bus cycle from the CPU.
When one stolen bus cycle displaces one instruction-time, the slowdown fraction is the number of DMA bus cycles stolen per second divided by the number of CPU instruction-times available per second.
Application
An 8-bit character occupies 1 byte, while a 32-bit word occupies 4 bytes.
Word-transfer rate = 4,800 characters/s ÷ 4 characters/word = 1,200 words/s.
At one stolen cycle per word, DMA steals 1,200 CPU instruction-times each second.
Slowdown = (1,200 ÷ 1,000,000) × 100% = 0.12%.
Cross-check
The CPU retains 1,000,000 − 1,200 = 998,800 instruction-times per second, which is 99.88% of its original rate. The lost fraction is therefore 100% − 99.88% = 0.12%.
Therefore, the CPU slowdown is 0.12%.
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