The chip select logic for a certain DRAM chip in a memory system design is…

Concept

A chip-select (CS) decoder makes an address line a fixed (decoded) bit only when the gate forces it to a single value; any address line NOT fed into the gate is a don't-care line that the chip ignores. For an AND-gate CS, every direct input must be 1 and every bubbled (inverted) input must be 0 for CS to assert. The number of don't-care lines k sets the block size 2k, while the decoded lines fix the base address.

Application

From the circuit, CS is the output of one AND gate whose inputs are A15, A14, A13 (bubbled), A12 (bubbled) and A11. For CS to be active, each input condition must be met:

1. A15 = 1 (direct input must be high).

2. A14 = 1 (direct input must be high).

3. A13 = 0 (bubbled input is inverted, so the line itself must be 0).

4. A12 = 0 (bubbled input is inverted, so the line itself must be 0).

5. A11 = 1 (direct input must be high).

So the top five lines are fixed as A15 A14 A13 A12 A11 = 1 1 0 0 1. Lines A10 down to A0 are not wired to the gate, so they are 11 don't-care lines.

Base address (all don't-cares = 0): the 16-bit pattern is 1100 1000 0000 0000 = C800 in hex. Top address (all don't-cares = 1): 1100 1111 1111 1111 = CFFF in hex.

Cross-check

With 11 don't-care lines the block size is 211 = 2048 = 800 in hex, so the window runs from C800 up to C800 + 7FF = CFFF, a 2 KB block. The enabled range is C800 to CFFF.