In a level-triggered SR flip-flop, if the Set (S) input receives a high signal…
2025
In a level-triggered SR flip-flop, if the Set (S) input receives a high signal while the Reset (R) remains low during the active clock level, what will be the effect on the output Q?
Answer: C. The output Q becomes 1 — In a level-triggered SR flip-flop, the output state is determined by the inputs S (Set) and R (Reset) whenever the clock signal is at its active level. When…
- A.
The output retains its previous value
- B.
The output Q becomes 0
- C.
The output Q becomes 1
- D.
The output toggles
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Correct answer: C
In a level-triggered SR flip-flop, the output state is determined by the inputs S (Set) and R (Reset) whenever the clock signal is at its active level. When the Set input S is high (logic 1) and the Reset input R is low (logic 0), the flip-flop enters its 'Set' state. This specific input combination forces the primary output Q to transition to logic 1, regardless of its previous state.
Therefore, Option C is correct because the high signal on S actively drives Q to 1 during the active clock level. Option A is incorrect because the output does not retain its value; it changes in response to the Set input. Option B is incorrect because Q becomes 0 only when S is low and R is high (Reset condition). Option D describes a T flip-flop behavior, not the standard SR operation where inputs directly set or reset the output.