Arrange the instruction cycle in correct sequence: A. Decode B. Store C. Fetch…

Concept: A CPU carries out each machine instruction as a fixed, repeating sequence of stages called the instruction cycle. In the four-stage form used in this question the stages are fetch, decode, execute and store (write-back). Each stage consumes the output of the stage before it: an instruction must be inside the CPU before it can be interpreted, its operation must be identified before it can be carried out, and a result must exist before it can be written anywhere. That dependency chain, not convention, is what fixes the order.

Application: Applying that chain to the four stages named in the stem:

1. Fetch — the control unit places the address held in the program counter on the address bus and copies the instruction stored at that address into the instruction register; the program counter is then advanced so that it points at the next instruction. Until this fetch completes, the instruction is not inside the CPU and nothing about it can be interpreted.

2. Decode — the control unit reads the opcode field of the instruction register, works out which operation is being requested, and locates its operands. This needs the bit pattern brought in by the fetch stage.

3. Execute — the ALU or the addressed functional unit performs the requested operation on those operands. This needs the operation to have already been identified by the decode stage.

4. Store — where the instruction produces a result, that result is written back to the destination register or memory location; this write-back completes the instruction. The CPU then begins the cycle again on the instruction the program counter now points at.

Read against the letters used in the stem, that sequence is Fetch (C), Decode (A), Execute (D), Store (B) — the arrangement C, A, D, B.

Cross-check: Test the three dependencies against any other arrangement of the four stages. Placing the 'Store' stage before the 'Execute' stage writes back a result that has not been produced yet; placing the 'Execute' stage before the 'Decode' stage carries out an operation the CPU has not yet identified; placing the 'Decode' stage before the 'Fetch' stage interprets an instruction that is not yet inside the CPU. Exactly one arrangement of the four survives all three tests, and it is the one derived above.