Given below are two statements : Statement I: Most PCs use Dynamic RAMs for…

Concept

Cache memory is designed to minimize the time between a processor request and data delivery. A cache therefore uses a memory technology with very low access latency.

SRAM stores each bit in a multi-transistor latch and does not need periodic refresh. DRAM uses a compact capacitor-based cell that must be refreshed, giving higher density and lower cost but longer access latency.

Application

Statement I is false. CPU caches in personal computers are ordinarily built from SRAM, not DRAM, because cache performance depends on rapid access near the processor.

Statement II is true. The larger SRAM cell uses more silicon area, so SRAM costs more per bit, while its latch-based operation makes it faster than DRAM.

Cross-check

The memory hierarchy places small, fast SRAM caches next to the CPU and larger, cheaper DRAM as main memory. This independently gives Statement I = false and Statement II = true.

Contrast

• Treating both statements as true places refresh-dependent DRAM in the usual CPU-cache role, despite the latency advantage of SRAM.

• Treating both statements as false overlooks the lower latency and higher per-bit cost created by SRAM latch cells.

• Treating Statement I as true and Statement II as false reverses both the usual cache technology and the SRAM–DRAM speed-cost trade-off.

• The remaining truth pattern follows from SRAM serving the low-latency cache role while costing more per bit than DRAM.

Result

Statement I is false, while Statement II is true.