Which of the following polynomials is used for the 16-bit frame check sequence…

Concept: a CRC treats the bits of a frame as the coefficients of a polynomial over GF(2) and divides that polynomial by a fixed generator polynomial G(x). The remainder of that division, after any transformation the protocol prescribes, is sent along with the frame as its frame check sequence (FCS). A remainder always has lower degree than the divisor, so a generator of degree n always yields an n-bit FCS, and each configured CRC/FCS mode fixes one specific G(x) so that sender and receiver divide by exactly the same divisor.

Application: for the 16-bit FCS variant represented by these choices, HDLC (High-Level Data Link Control, standardised as ISO/IEC 13239 and derived from ISO 3309) uses the CRC-CCITT generator x16 + x12 + x5 + 1. Its coefficient word is 1 0001 0000 0010 0001; dropping the implicit leading x16 term leaves the familiar hexadecimal shorthand 0x1021.

In the bare polynomial-division model the FCS is produced like this:

1. Because the generator has degree 16, append exactly 16 zero bits to the address, control and information bits of the frame.

2. Divide that extended bit string by the divisor word 10001000000100001 using modulo-2 (XOR) division.

3. Replace the appended zeros with the 16-bit remainder; in this bare model that remainder is the frame check sequence.

4. A receiver that divides the received frame together with its FCS by the same generator then obtains a zero remainder whenever no error is detected.

The HDLC FCS-16 procedure layers three conventions on top of this bare model: the CRC register is preset to all ones, the computed value is transmitted as its ones-complement, and the bits go out least-significant-bit first. Those conventions change the value a real receiver compares against, which RFC 1662 gives as the good-frame residue 0xF0B8, but they do not change the generator polynomial, and it is the generator that this question asks for.

Cross-check: the degree of a generator fixes the width of the FCS it can produce, and the FCS-16 field is 16 bits wide, so degree alone narrows the four candidates to two and the tap positions settle the rest.

The two degree-8 generators can only produce an 8-bit FCS, so neither can fill the HDLC FCS-16 field. Of the two degree-16 candidates, x16 + x12 + x4 + 1 has its middle tap at x4 and so encodes 0x1011, which is not the generator specified for HDLC FCS-16, while x16 + x12 + x5 + 1 is exactly the CRC-CCITT divisor 0x1021 that ISO/IEC 13239 specifies for HDLC FCS-16.

Result: for the HDLC FCS-16 variant represented by these choices, the CRC generator is x16 + x12 + x5 + 1.