The ADD micro-operation in the register transfer R1 ← R2 + R3 takes place in…
2026
The ADD micro-operation in the register transfer R1 ← R2 + R3 takes place in which of the following?
- A.
MAR loading phase
- B.
ALU execution phase
- C.
Operand fetch phase
- D.
None of these
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Correct answer: B
Micro-operations are the elementary operations performed on the data held in CPU registers during one clock cycle of the instruction cycle.
Register transfer: moving the contents of one register into another without changing the values.
Arithmetic: combining register contents using operations such as addition, subtraction, or increment.
Logic: applying bit-wise Boolean operations such as AND, OR, XOR, and NOT to register contents.
Shift: moving the bits held in a register one or more positions left or right.
Arithmetic micro-operations such as ADD, SUBTRACT, and INCREMENT are always carried out by the Arithmetic Logic Unit (ALU), which is invoked during the execute phase of the instruction cycle.
Classify the operation: R1 <- R2 + R3 combines the contents of two registers, R2 and R3, using addition, so it belongs to the arithmetic category rather than the register-transfer or shift category.
Trace the instruction cycle: after the instruction is fetched and decoded, the control unit gates the contents of R2 and R3 onto the internal buses so that they are ready as inputs; this operand-preparation step only moves the bit patterns forward, it does not combine them.
Locate the addition: the ALU receives R2 and R3 as its two inputs during the execute phase, its adder circuitry forms the sum, and the control unit then transfers that sum into R1; this is the exact point where the ADD micro-operation is carried out.
Conclude: since the hardware that combines R2 and R3 is the ALU, and it operates during the execute step of the cycle, the ADD micro-operation R1 <- R2 + R3 takes place in the ALU execution phase.
Phase | Role in the instruction cycle |
|---|---|
MAR loading | Places a computed address into the Memory Address Register ahead of a memory read or write; R1 <- R2 + R3 references no memory location, so no operand values are combined here. |
Operand fetch | Gates the source registers onto the internal buses so their values are ready as inputs; the buses carry the values forward without combining them. |
ALU execution | Receives the operand values as inputs and forms the arithmetic result inside the ALU's adder circuitry. |
Hence the ADD micro-operation in R1 <- R2 + R3 takes place in the ALU execution phase.