What is the main advantage of instruction pipelining?

Instruction pipelining splits instruction execution into stages (fetch, decode, execute, memory access, write-back) and overlaps these stages across successive instructions, so a new instruction enters the pipeline before the previous one has fully finished. Because several instructions are in flight simultaneously, the average time to complete each instruction, and hence overall throughput, improves, even though a single instruction's total latency through all stages is unchanged.

Applying this here: the direct effect of that stage-overlap is a lower average completion time per instruction, which is exactly what makes 'Reduced instruction execution time' the main advantage being asked about.

Checking each other option against this by value:

• Increased memory access speed, a cache/RAM property, not something pipelining's stage-overlap changes.

• Improved data transfer rate, a bus/interconnect bandwidth property, again unrelated to overlapping instruction stages.

• All of these, fails because the two properties above are unaffected by pipelining, so grouping them with execution time overstates pipelining's effect.