Consider an instruction pipeline with four stages (S1, S2, S3 and S4), each…
2025
Consider an instruction pipeline with four stages (S1, S2, S3 and S4), each with a combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the following figure:
What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?
- A.
4.0
- B.
2.5
- C.
1.1
- D.
3.0
Attempted by 44 students.
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Correct answer: B
In a non-pipeline implementation, the total time to execute one instruction is simply the sum of all stage delays. Here, that equals 5 + 6 + 11 + 8 = 30 nanoseconds. In a pipelined system, the clock cycle time is determined by the slowest stage plus the overhead of the pipeline registers. The maximum stage delay is 11 ns, and with a register delay of 1 ns, the clock cycle becomes 12 ns. Under ideal steady-state conditions, one instruction completes every clock cycle. Therefore, the speedup is calculated by dividing the non-pipeline time per instruction by the pipeline clock cycle: 30 / 12 = 2.5. Option A (4.0) incorrectly assumes ideal speedup equals the number of stages without considering register overhead or uneven stage delays. Option D (3.0) might result from ignoring the register delay, calculating 30/10, which is incorrect. Thus, the correct speedup is approximately 2.5.