Consider an instruction pipeline with four stages (S1, S2, S3 and S4), each…

Concept

In a pipeline whose stages take unequal amounts of time, the pipeline's clock cycle time is fixed by the slowest stage plus the delay of the pipeline register (latch) that follows it -- every stage must wait for the longest stage to finish and for the register to latch its output before the next cycle can start. Once the pipeline is full (steady state), one instruction completes every clock cycle, so the achievable speedup over a non-pipelined implementation is the ratio of the total non-pipelined execution time to this single pipeline clock cycle time.

Application

1. Non-pipelined execution time per instruction is the sum of all four stage delays: 5 + 6 + 11 + 8 = 30 ns.

2. The slowest stage is S3, with a delay of 11 ns.

3. The pipeline clock cycle equals the slowest stage delay plus the pipeline-register delay: 11 + 1 = 12 ns.

4. Steady-state speedup equals the non-pipelined time divided by the pipeline clock cycle: 30 / 12 = 2.5.

Cross-check

If all four combinational stages had the same delay d, the speedup with a 1 ns register overhead would be 4d / (d + 1), approaching the stage-count ceiling of 4 only when the register overhead is negligible relative to d. Here the unequal stage delays make the 11 ns stage the bottleneck, and substituting the actual 12 ns clock interval gives 30 / 12 = 2.5.