Asynchronous buses rely on handshaking primarily because

Concept

An asynchronous bus has no shared clock between the bus master and the connected devices. Instead, the transfer is coordinated through explicit control lines — a request signal from the master and an acknowledge/ready signal from the target — and the transfer completes only once this signal exchange, or "handshake", is complete. This protocol exists because different devices on the same bus can take a different, and sometimes non-deterministic, amount of time to respond to a request.

Application

1. The bus master asserts a request line to begin a transfer with a target device.

2. The target device takes however long it internally needs — a duration that can differ from one device to another and even from one transfer to the next on the same device — before it can supply or accept the data.

3. Once ready, the target asserts an acknowledge/ready line back to the master.

4. Only after observing this acknowledge signal does the master latch the data or start the next step of the transfer.

5. Because completion is signalled explicitly rather than assumed after a fixed number of clock cycles, the protocol works correctly no matter how long any individual device takes to respond.

Cross-check

• A basic, fixed-timing synchronous bus assumes every transfer completes within a fixed, pre-agreed number of clock cycles referenced to a shared clock; more elaborate synchronous designs add wait-state cycles for slower devices, but these too are still sampled relative to that shared clock. An asynchronous bus, in contrast, has no shared clock at all — timing is governed purely by the request/acknowledge signal exchange itself, which is what lets any device's response time be genuinely unpredictable without breaking the protocol.

• Clock skew — the difference in arrival time of the same clock edge at different points in a circuit — is a synchronous-design timing-margin issue handled through clock-tree design, unrelated to whether a bus uses handshaking.

• Cache-coherence mechanisms keep cache and memory contents consistent, a memory-hierarchy concern separate from bus-transfer completion signalling.

• Since the mechanism exists to accommodate devices whose response time is not fixed or guaranteed in advance, this confirms that handshaking is used because devices have unpredictable response time.