What is the main characteristic of Cycle Stealing in Direct Memory Access?
2025
What is the main characteristic of Cycle Stealing in Direct Memory Access?
- A.
The DMA controller temporarily borrows the system bus for a single cycle during CPU idle time.
- B.
The CPU and DMA controller execute simultaneously without interference.
- C.
The CPU and DMA controller share the same clock cycle for data transfer.
- D.
The DMA controller halts the CPU until the entire data transfer is completed.
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Correct answer: A
In Cycle Stealing, the I/O device operates much slower than the memory or the CPU. It prepares one byte or word of data at a time. The process follows a highly fast cycle:
The Request: The DMAC senses that one word of data is ready for transfer and issues a bus request (BR) to the CPU.
The Grant: The CPU finishes its current clock cycle, releases control of the buses, and replies with a bus grant (BG).
The Theft: The DMAC "steals" exactly one bus cycle to transfer that single word directly to memory.
The Release: The DMAC immediately drops the bus request, handing control right back to the CPU.