In a positive-edge-triggered JK flip-flop, if J and K both are high then the…
2016
In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be ______ on the rising edge of the clock.
- A.
No change
- B.
Set
- C.
Reset
- D.
Toggle
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Correct answer: D
When J and K inputs are both high (logic 1) in a JK flip-flop, the output toggles state on the active clock edge. This means if Q was 0 it becomes 1, and if Q was 1 it becomes 0.
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