In RS flip-flop, the output of the flip-flop at time (t+1) is same as the…
2018
In RS flip-flop, the output of the flip-flop at time (t+1) is same as the output at time t, after the occurance of a clock pulse if :
- A.
S=R=1
- B.
S=0, R=1
- C.
S=1, R=0
- D.
S=R=0
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Correct answer: D
Answer: S=0, R=0
Reason: When both set and reset inputs are 0, neither action is asserted, so the flip-flop does not change state. Thus the output after the clock pulse equals the previous output (Q(t+1) = Q(t)).
S=1, R=0: Set is asserted → output becomes 1 (state changes).
S=0, R=1: Reset is asserted → output becomes 0 (state changes).
S=1, R=1: For the standard NOR-based RS flip-flop this is an invalid/indeterminate condition and does not define a stable next state.
Therefore, the hold (no-change) condition is when both inputs are 0.
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