A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D),…
2024
A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions?
- A.
10
- B.
14
- C.
15
- D.
19
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Correct answer: B
Answer: 14 cycles.
Reason: count pipeline fill and steady-state completion rate.
First instruction takes 5 cycles to pass through Fetch, Decode, Execute, Memory, and Write-back.
After the pipeline is filled, one instruction completes per cycle (steady-state throughput of 1 instruction/cycle).
For 10 instructions: total cycles = number of stages + (number of instructions − 1) = 5 + (10 − 1) = 14.
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