Pipelining improves performance by :

Answer: Pipelining improves performance by exploiting instruction-level parallelism.

Key idea: Split each instruction into a sequence of stages (for example: fetch, decode, execute, memory, write-back) and overlap the stages of multiple instructions so several instructions are in different stages at the same time.

• Effect on performance: increases throughput (instructions completed per unit time). After the pipeline is filled, an ideal pipeline can complete about one instruction per cycle, greatly improving overall instruction throughput.

• Effect on latency: does not reduce the latency of a single instruction. The time for one instruction to go through all stages is roughly the same (or slightly higher due to register overhead). Pipelining focuses on throughput, not single-instruction latency.

• Hazards and cache behavior: pipelining does not eliminate data hazards (these still need handling via forwarding, stalls, or reordering). It also does not change the cache miss rate, which depends on memory access patterns and cache design.

Therefore, the most accurate description of what pipelining improves is exploiting instruction-level parallelism to increase instruction throughput.