The Reduced Instruction Set Computer (RISC) characteristics are: (a) Single…

Answer: Single cycle instruction execution and Efficient instruction pipeline.

• Why single cycle instruction execution is considered a RISC characteristic: RISC designs use a small set of simple instructions that are intended to be executed quickly (often in one cycle), which simplifies control logic and helps achieve higher clock rates.

• Why variable-length instruction formats are not RISC: RISC architectures normally use fixed-length instructions to make instruction fetch and decode simpler and to facilitate pipelining.

• Why instructions that manipulate operands in memory are not RISC: RISC follows a load/store (register-to-register) model: only explicit load and store instructions access memory; arithmetic and logical operations operate on registers.

• Why efficient instruction pipeline is a RISC characteristic: The regular, simple instruction set and fixed formats enable deep, efficient pipelining and high instruction throughput.

Summary: The correct characteristics are single cycle instruction execution and efficient instruction pipeline because RISC focuses on simple, fixed-format instructions and a load/store architecture that together enable efficient pipelining and fast instruction execution.